The present invention relates to integrated circuits and, more particularly, to a low power State Retention Power Gating (SRPG) cell for an integrated circuit.
In order to reduce power consumption, certain devices may be placed in a low-power mode when not active. Some circuits may be deactivated when not in use by shutting down the power supply to the circuit and placing the circuit in a power-saving mode. Shutting down the power supply can reduce leakage currents, leading to an overall reduction in power consumption by the device.
For some circuits, it may be necessary to preserve logic values while the component is deactivated. State Retention Power Gating (SRPG) describes an arrangement in which a subset of the components of the circuit remain powered during a deactivation period in order to retain or preserve the logic state of the circuit, while the remaining components are powered-down.